A Delay Locked Loop (DLL) with an adjustable delay line is used to synchronize a first clock signal with a second clock signal by delaying the first clock signal. The DLL includes a phase detector, which detects the phase difference between the first clock signal and the second clock signal. Based on the detected phase difference, the DLL synchronizes the first clock signal to the second clock signal by adding an appropriate delay to the first clock signal until the second clock signal is in phase with the first clock signal.
FIG. 1 is a block diagram of a prior art DLL 100. An externally supplied clock (CLK) is buffered by clock buffer 101 to provide a reference clock (CLK_REF) that is coupled to a voltage controlled delay line 102 and a phase detector 104. The voltage controlled delay line 102 produces an output clock (CLK_OUT), which is a delayed version of CLK_REF and is routed to various circuits within the device and to the replica delay circuit 103. The replica delay circuit 103 provides a delay similar to the delay through buffer 101 and wire routing delays. Replica delays, otherwise known as delay model circuits, are well-known to those skilled in the art. See U.S. Pat. No. 5,796,673 to Foss et al. for further explanation of replica delays. A feedback clock signal CLK_FB output from the replica delay circuit 103 is coupled to the phase detector 104. Other prior art DLLs use a digital tapped delay line. Commonly owned U.S. Pat. Nos. 5,796,673 and 6,087,868 describe such types of DLLs.
The phase detector 104 generates phase control signals (UP, DOWN) dependent on the phase difference between CLK_REF and CLK_FB. The UP signal is set to a logic ‘1’ on first receipt of a CLK_REF rising edge and the DOWN signal is set to a logic ‘1’ on first receipt of a CLK_FB rising edge. Both UP and DOWN signals are reset to logic ‘0 ’ when the subsequent rising edge of the two signals is received. Thus, when the CLK_REF rising edge is detected before the CLK_FB rising edge, the UP signal transitions to a logic ‘1’ to increase the delay in the voltage controlled delay line (VCDL) 102 until the next rising edge of the CLK_FB is detected. Alternatively, if CLK_FB rising edge is detected prior to the CLK_REF rising edge, the DOWN signal transitions to a logic ‘1’ to decrease the delay until the next rising edge of CLK_REF is detected.
The phase control signals (UP/DOWN) of the phase detector 104 are integrated by a charge pump 105 and a loop filter 106 to provide a variable bias voltage VCTRL 110. The bias voltage VCTRL selects the delay to be added to CLK_REF by the VCDL 102 to synchronize CLK_FB with CLK_REF.
FIG. 2 is a schematic of a prior art charge pump 200 that can be used in the prior art DLL shown in FIG. 1. Referring to the DLL system shown in FIG. 1, the response of the DLL is determined in part by the ability to precisely control the control voltage VCTRL which controls the voltage control delay 102 (FIG. 1) in the DLL. This is turn is determined by how precisely current can be added to or drained from the OUT node of the charge pump 200.
The voltage at the OUT node of the charge pump 200 is dependent on the phase control signals (UP/DOWN) received from the phase detector 104 (FIG. 1). To decrease the delay, the DOWN signal and ENABLE signal are both asserted (logic ‘1’) which results in a logic ‘1’ at the gate of transistor 217 turning transistor 217 ‘on’. With transistor 215 already ‘on’, current (pull-down current) flows from node OUT to ground through transistor 215 and transistor 217. This pull-down current drains the charge from the OUT node, causing the voltage at the OUT node to decrease.
To increase the delay, the UP signal and the ENABLE signal are both asserted (logic ‘1’) which results in a logic ‘0 ’ at the gate of transistor 209, turning transistor 209 ‘on’. With both transistor 209 ‘on’ and transistor 210 ‘on’, current flows from Vdd through transistor 209 and transistor 210 to the OUT node. This current flows through the loop filter 106 (FIG. 1) and adds charge to node OUT. The added charge increases the voltage at the OUT node.
The charge pump 200 includes two current mirrors labeled M1, M2 that control the magnitude of the current provided to the OUT node of the charge pump 200. Current mirror M1 includes master transistor 214 and slave transistors 210 and 212 and controls the pull-up current flowing from Vdd through transistor 210. Current mirror M2 includes master transistor 216 and slave transistor 215. Transistor 216 takes the current from transistor 212 in current mirror M1 and mirrors it in transistor 215 to provide the pull-down current through transistor 215 to ground.
While the DLL is in lock condition, the phase detector 104 (FIG. 1) typically asserts its UP and DOWN signals for equal durations on every clock cycle. Thus, the charge pump 200 will receive both UP and DOWN signals asserted for an equal period of time in order to maintain the same voltage at the node OUT. In order to provide zero static phase offset at the output of the DLL when both the UP and DOWN signals of the phase comparator are asserted for equal durations, the charge pump must produce the same current pulses at the output OUT (node OUT) so that the current pulses cancel out and no net charge change is delivered to the loop filter 106 (FIG. 1).
Thus, in order to minimize the static phase error, the drain/source currents through transistor 210 and transistor 215 should be matched as closely as possible. Ideally the magnitudes of the currents through transistors 210 in current mirror M1 and transistor 215 in current mirror M2 are identical. The current matching is performed by mirroring the current from device 212 into device 210 and down to device 215 via current mirror M2.
However, the voltage at node OUT may not be the same as the voltage at node ‘ctrl’. This voltage difference results in the drain-source voltage of bias transistor 216 in current mirror M2 being different from the drain-source voltage of transistor 215. The same is true for transistor 212 and transistor 210 with respect to the drain-source voltage of bias transistor 214 in current mirror M1. A change in the source-drain voltage leads to a change in the drain current especially if transistors 215 and 210 have low output impedance. This results in a different drain/source current flowing through the devices in each current mirror, which finally results in a current difference between transistor 210 and transistor 215. The difference in current between transistor 215 and transistor 210 can be as large as about 20% which results in a significant static phase error when the DLL is in lock condition. In the embodiment shown, the static phase error increases as technologies become smaller because the output impedance of transistors becomes smaller.
The DLL static phase error is understood as a constantly occurring phase difference between CLK_REF and CLK_FB when the DLL is in lock condition, and the charge supplied to node OUT through transistor 210 is equal to the charge drained from node OUT through transistor 215 during every clock cycle. Thus, the phase detector detects that the clock signals are perfectly aligned and does not vary the voltage level at node OUT.
FIG. 3 is a graph that illustrates source and sink current in the prior art DLL shown in FIG. 2 prior to lock condition. Trace 150 corresponds to the source current through transistor 210 in FIG. 2 and trace 152 corresponds to the sink current through transistor 215 in FIG. 2. Prior to lock condition, the source current and the sink currents are not equal, with the source current being greater than the sink current. In lock condition, the areas below each of the traces 150, 152 will be the same. Thus, when the currents are not equal, the DLL compensates with a phase error, or “static phase error” in order to maintain the same charge in the node OUT. The phase error results from the signal with a lower current being wider in time than the signal with the higher current so that the areas are substantially equal. Although the falling edge of each of the traces 150, 152 will occur at about the same time, the rising edges will occur at different times to compensate for the non-equal source and sink current. Therefore the phase error is present by the inherent design of the prior art DLL.
In submicron technologies (i.e., 0.13 microns and smaller) the output impedance of a transistor decreases as the channel length shrinks, so the transistors do not meet the requirements for the output impedance required for an output transistor of a charge pump. One known method of increasing the output impedance of the charge pump in order to minimize static phase error is through the use of a cascode current source. However, a cascode current source does not fit well with the trend of power supply voltage decrease. For example, with power supply voltage of 1V and typical threshold voltage of 0.25V to 0.3V, a 1V power supply voltage is too low to sustain two cascode current sources (each having two threshold voltages) in series.